1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device.
Priority is claimed on Japanese Patent Application No. 2009-145326, filed Jun. 18, 2009, the content of which is incorporated herein by reference.
2. Description of the Related Art
Conventionally, LSI (Large Scale Integration) circuits have been used for main parts of computers, electronic devices, and the like. In an LSI circuit, multiple MOS transistors, resistors, and the like are integrated on a chip. Since LSI circuits are used for various purposes, diverse product demand has been required to be satisfied especially for embedded DRAM (Dynamic Random Access Memory) to be provided on an LSI circuit.
To satisfy the diverse product demand, Japanese Patent Laid-Open Publication No. H05-102428 discloses a method of manufacturing a semiconductor device including a memory cell portion and a peripheral cell portion which have different widths of LDD (Lightly Doped Drain) regions. Japanese Patent Laid-Open Publication No. 2005-136434 discloses a method of siliciding only a peripheral circuit region requiring a high-speed operation. As a method of changing memory cell performance, Japanese Patent Laid-Open Publication No. 2003-282823 discloses a method of forming a high-voltage portion, a peripheral cell portion, and a memory cell portion, which have different transistor structures.
Japanese Patent Laid-Open Publication No. H11-097649 discloses a method of selectively forming a silicide layer in order to prevent refresh defects. As a method of forming different transistor structures on a semiconductor substrate, Japanese Patent Laid-Open Publication No, 2000-232076 discloses a method of forming a silicide layer only for a gate electrode requiring a high-speed operation, and of embedding both a normal transistor structure and an elevated source-and-drain structure on a semiconductor substrate.
Not only diversification, but also miniaturization are required for LSI circuits, especially for DRAM. However, the method of selectively forming a silicide layer when forming a contact plug for a MOS transistor is likely to cause an increase in junction leakage. This is because a silicide layer, which is close to a main surface of a semiconductor substrate, has defects, and therefore junction leakage is likely to increase if an edge of the silicide layer becomes close to an edge of a PN junction. For this reason, a contact plug for the MOS transistor has had to be distanced in the gate-length direction from the edge of the PN junction in an impurity diffusion region formed in the semiconductor substrate, in plan view. In other words, a contract plug for a MOS transistor has had to be distanced from a sidewall layer covering a sidewall of a gate electrode, thereby requiring a gate length, and therefore preventing miniaturization of semiconductor devices.
To prevent the increase in junction leakage, i.e., the short channel effect, a MOS transistor having an elevated source-and-drain structure is effective. A MOS transistor having the elevated source-and-drain structure is formed by forming an impurity diffusion region in a silicide layer (epitaxial growth layer) and thus forming a doped epitaxial growth layer. Since the impurity diffusion region is formed in the doped epitaxial growth layer, the depth of the impurity diffusion region adjacent to the main surface of the semiconductor substrate can be reduced more than in the case of a normal MOS transistor. For this reason, the MOS transistor having the elevated source-and-drain structure can decrease the gate length while preventing the short channel effect.
However, regarding the MOS transistor having the elevated source-and-drain structure, the silicide layer (epitaxial growth layer), which includes the impurity diffusion region, is positioned higher in level than a main surface of the semiconductor substrate. For this reason, parasitic capacitance between the impurity diffusion region and the gate electrode is greater than that of a MOS transistor having a normal structure. Therefore, high-frequency response characteristics of the MOS transistor having the elevated source-and-drain structure is likely to degrade compared to that of the MOS transistor having the normal structure.
Further, the method of embedding both a MOS transistor having the normal structure and a MOS transistor having the elevated source-and-drain structure in a semiconductor substrate complicates the manufacturing processes.